A Customized MVA Model for ILP Multiprocessors

In each submodel, the memory system is viewed as a system of queues (e.g., the memory bus, DRAM modules and associated directories, and network interfaces) and delay centers (e.g., switches in the interconnection network). We create a set of intuitive customized mean value analysis (CMVA) equations to obtain estimates of throughput (instructions per cycle) in each submodel. The CMVA technique has proven to be accurate in validation experiments for a number of simpler architectural models [9].